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MSP430F14X Datasheet(PDF) 35 Page - Texas Instruments |
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MSP430F14X Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 88 page  35 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 www.ti.com SLAS272H – JULY 2000 – REVISED MAY 2018 Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated (1) Multiple source flags (2) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. (3) Timer_B7 in the MSP430F14x(1) MCUs has 7 CCRs, and Timer_B3 in the MSP430F13x MCUs has 3 CCRs. In Timer_B3, there are only interrupt flags TBCCR0, TBCCR1, and TBCCR2 CCIFGs and the interrupt-enable bits TBCCTL0, TBCCTL1, and TBCCTL2 CCIEs. (4) Interrupt flags are located in the module. (5) ADC12 is not implemented on the MSP430F14x1 devices. 6.4 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6-3. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power up External reset Watchdog Flash memory WDTIFG KEYV(1) Reset 0FFFEh 15, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG(1) (Non)maskable(2) 0FFFCh 14 Timer_B7(3) TBCCR0 CCIFG(4) Maskable 0FFFAh 13 Timer_B7(3) TBCCR1 to 6 CCIFGs, TBIFG(1)(4) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF9h 11 Watchdog timer WDTIFG Maskable 0FFF4h 10 USART0 receive URXIFG0 Maskable 0FFF2h 9 USART0 transmit UTXIFG0 Maskable 0FFF0h 8 ADC12(5) ADC12IFG(1)(4) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG(4) Maskable 0FFECh 6 Timer_A3 TACCR1 CCIFG, TACCR2 CCIFG, TAIFG(1)(4) Maskable 0FFEAh 5 I/O port P1 (eight flags) P1IFG.0 to P1IFG.7(1)(4) Maskable 0FFE8h 4 USART1 receive URXIFG1 Maskable 0FFE6h 3 USART1 transmit UTXIFG1 Maskable 0FFE4h 2 I/O port P2 (eight flags) P2IFG.0 to P2IFG.7(1)(4) Maskable 0FFE2h 1 – – – 0FFE0h 0, lowest 6.5 Bootloader (BSL) The MSP430 BSL lets users program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory through the BSL is protected by a user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430™ Flash Device Bootloader (BSL) User's Guide. Table 6-4 lists the pin requirements for the BSL. Table 6-4. BSL Pin Requirements and Functions BSL FUNCTION PM, PAG, AND RTD PACKAGE PINS Data transmit 13 - P1.1 Data receive 22 - P2.2 |
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