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MSP430F14X Datasheet(PDF) 49 Page - Texas Instruments |
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MSP430F14X Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 88 page ![]() P2IN.x P2OUT.x Pad Logic P2DIR.x P2SEL.x Module X OUT Edge Select Interrupt P2SEL.x P2IES.x P2IFG.x P2IE.x P2IRQ.x Direction Control P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6/ADC12CLK P2.7/TA0 0 1 0 1 Interrupt Flag Set EN Q Module X IN EN D Bus Keeper CAPD.X 0: Input 1: Output From Module 49 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 www.ti.com SLAS272H – JULY 2000 – REVISED MAY 2018 Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated (1) Signal to Timer_A (2) Signal from Comparator_A (3) ADC12CLK signal is output of the 12-bit ADC module (4) Signal from Timer_A 6.9.2 Port P2, Input/Output With Schmitt Trigger Figure 6-11. Port P2 (P2.0 to P2.2, P2.6, and P2.7) Diagram Table 6-17. Port P2 (P2.0 to P2.2, P2.6, and P2.7) Pin Functions PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.0 P2DIR.0 P2DIR.0 P2OUT.0 ACLK P2IN.0 unused P2IE.0 P2IFG.0 P2IES.0 P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 DVSS P2IN.1 INCLK(1) P2IE.1 P2IFG.1 P2IES.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 CAOUT(2) P2IN.2 CCI0B(1) P2IE.2 P2IFG.2 P2IES.2 P2Sel.6 P2DIR.6 P2DIR.6 P2OUT.6 ADC12CLK(3) P2IN.6 unused P2IE.6 P2IFG.6 P2IES.6 P2Sel.7 P2DIR.7 P2DIR.7 P2OUT.7 Out0 signal(4) P2IN.7 unused P2IE.7 P2IFG.7 P2IES.7 |
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