MSP430F14X datasheet(41/88 Pages) TI2

41 / 88 page

MSP430F149, MSP430F148, MSP430F147

MSP430F1491, MSP430F1481, MSP430F1471

MSP430F135, MSP430F133

www.ti.com

SLAS272H – JULY 2000 – REVISED MAY 2018

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MSP430F135 MSP430F133

Detailed Description

6.8.8

ADC12 (MSP430F14x and MSP430F13x Only)

The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit

SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The

conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored

without CPU intervention.

6.8.9

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing (see Table 6-12). Timer_A3 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

Table 6-12. Timer_A3 Signal Connections

INPUT PIN NUMBER

DEVICE INPUT

SIGNAL

MODULE INPUT

NAME

MODULE BLOCK

MODULE OUTPUT

SIGNAL

OUTPUT PIN

NUMBER

12 - P1.0

TACLK

Timer

ACLK

SMCLK

21 - P2.1

TAINCLK

INCLK

13 - P1.1

TA0

CCI0A

CCR0

TA0

13 - P1.1

22 - P2.2

TA0

CCI0B

17 - P1.5

DVSS

GND

27 - P2.7

DVCC

VCC

14 - P1.2

TA1

CCI1A

CCR1

TA1

CAOUT (internal)

CCI1B

DVSS

GND

DVCC

VCC

15 - P1.3

TA2

CCI2A

CCR2

TA2

ACLK (internal)

CCI2B

DVSS

GND

DVCC

VCC

6.8.10 Timer_B3 (MSP430F13x Only)

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple

capture/compares, PWM outputs, and interval timing (see Table 6-13). Timer_B3 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

6.8.11 Timer_B7 (MSP430F14x and MSP430F14x1 Only)

Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple

capture/compares, PWM outputs, and interval timing (see Table 6-13). Timer_B7 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

MSP430F14X Datasheet(PDF) 41 Page - Texas Instruments

MSP430F14X Datasheet(HTML) 41 Page - Texas Instruments

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