25CS160-HSLASHST datasheet(25/53 Pages) MICROCHIP

25 / 53 page

 2026 Microchip Technology Inc. and its subsidiaries

Preliminary

DS20007008B-page 25

25CS160

FIGURE 8-2:

PAGE WRITE SEQUENCE

8.2

Error Correction Code (ECC)

Architecture

The 25CS160 incorporates a built-in Error Correction

Code (ECC) logic scheme. The EEPROM array is

internally organized as one byte plus an additional

4 ECC parity bits of EEPROM. These 12 bits are

referred to as the internal physical data word. During a

read sequence, the ECC logic compares each physical

data byte with its corresponding four ECC parity bits. If

a single bit out of the 1-byte region happens to read

incorrectly, the ECC logic will detect the bad bit and

replace it with a correct value before the data are

serially clocked out. This architecture significantly

improves the reliability of the 25CS160 compared to a

device that does not utilize ECC.

8.3

Polling Routine

A polling routine can be implemented to optimize

time-sensitive applications that would prefer not to wait

the fixed maximum write cycle time (TWC). This method

allows the application to query whether the Serial

EEPROM has completed the write sequence. This

polling routine should be initiated once the internally

timed write sequence has begun.

The polling routine involves repeatedly sending the

Read

STATUS

(RDSR) instruction to

determine if the device has completed its self-timed

internal write cycle (see Figure 8-3). If the RDY/BSY

bit = 1 from RDSR, the write cycle is still in progress. If

RDY/BSY bit = 0 from RDSR, this indicates the write

cycle has ended. If the device is still in a busy state, the

RDSR instruction can be repeatedly executed until the

RDY/BSY bit = 0, signaling that the device is ready to

execute a new instruction. Only the RDSR instruction is

enabled during the write cycle.

FIGURE 8-3:

POLLING FLOW

SCK

234

567

Data In Byte n (32 max.)

MSb

0 0000 0 1 0 X X X

AA A

WRITE Opcode (02h)

Address Bits A15-A0

Data In Byte 1

MSb

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

825

TWC(1)

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

YES

Send Valid Write

Sequence

Deassert CS High to

Initiate a Write Cycle

Send

RDSR

Instruction to the Device

Next Sequence

Is RDY/BSY = 0?

25CS160-H/ST Datasheet(PDF) 25 Page - Microchip Technology

25CS160-H/ST Datasheet(HTML) 25 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL