25CS160-HSLASHST datasheet(30/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 30

25CS160

10.0 PROGRAMMABLE

UNDERVOLTAGE LOCKOUT

The 25CS160 is equipped with an undervoltage

lockout detection circuit, which looks for brown-out

events or device VCC power supply levels deemed too

low for a given application.

To prevent spurious application events that could

negatively affect the EEPROM contents of the device,

the 25CS160 employs a circuit that monitors the VCC

line voltage. Because the safe power supply voltage

level will vary by application, the threshold that defines

a brown-out event can be modified in the device from

the default level.

10.1

Undervoltage Lockout Detection

The

25CS160

contains

nonvolatile,

8-bit

Undervoltage Lockout Detection (UVLO) register that

can be modified to change the undervoltage detection

threshold (VUVL). When the detector is enabled (bit 5

must be set to logic ‘1’), the device will sample the VCC

supply level upon the detection of the CS pin going

high (which starts the internal write cycle) and

compare it to VUVL. If VCC remains below VUVL for the

minimum UVLO detection time (TUVL) after the CS

goes high, the UVLO detection circuit will inhibit the

write operation. The WLS bit in the STATUS register

can be checked to determine if the previous write

sequence was inhibited. If the WLS bit is a logic ‘1’,

VCC was less than VUVL, and the previous write

sequence was inhibited. The WLS bit is only valid if

the UVLO function is enabled. See Section 6.0

“STATUS Register” for more details.

The instructions that will be inhibited include the

following:

• WRITE, WRSR, WREX, LOCK, WUVL

The UVLO register has one bit (UVLOEN) that

controls if the undervoltage detection function is

enabled. Five other bits (VUVL[4:0]) determine the

undervoltage threshold level. Refer to Table 1-1 for the

specific threshold levels.

The STATUS register contains a volatile bit called

Write Lockout State (WLS, byte 1, bit 2). In the event

that a write sequence to nonvolatile memory is inhib-

ited by the undervoltage lockout detector circuit, the

WLS bit will read out as a logic ‘1’.

The WLS bit will continue to read out a logic ‘1’ until

one of the following occurs:

• A Power-On Reset (POR) event occurs

(Section 1.1.1, Device Power-On Reset)

• A nonvolatile write opcode is sent to the device

(WRITE, WRSR, WREX, LOCK, WUVL)

• A Software Device Reset (SRST) instruction is

executed

The organization of the register is depicted below in

Note:

If the STATUS register is read during the

UVLO detection time (TUVL), the device

will report a busy state, indicated by

RDY/BSY = 1. If the write is inhibited due

to the UVLO, the RDY/BSY bit will clear,

and the WLS bit will be set.

Note:

Setting the undervoltage detection thresh-

old (VUVL) above VCC will cause all write

sequences to be ignored. VCC must be

above VUVL to reprogram the VUVL.

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