25CS160-HSLASHST datasheet(26/53 Pages) MICROCHIP

26 / 53 page

 2026 Microchip Technology Inc. and its subsidiaries

Preliminary

DS20007008B-page 26

25CS160

9.0

SECURITY REGISTER

The Security register is segmented into one 32-byte

read-only page and one 32-byte user-programmable,

lockable ID page. The user-programmable, lockable ID

page supports both byte write and page write

sequences. The user-programmable, lockable ID page

may be permanently locked at any time with the LOCK

instruction. The Security register lock state can be

verified at any time with CHLK instruction.

9.1

Reading from the Security

Reading the Security register contents from the

25CS160 follows a similar sequence to reading the

EEPROM, but a different opcode and specific address

data are required. To read the Security register, first

drive the CS low to select the device, then send the

RDEX (83h) instruction via the SI line, followed by the

16-bit address to be read.

Upon completion of the 16-bit address, any data on the

SI line will be ignored. The data (D7-D0) at the

specified address are then shifted out onto the SO line.

If only one byte is to be read, the CS line should be

driven high after the data are output. The read

sequence can be continued since the byte address is

automatically incremented, and data will continue to be

shifted out. When the highest address is reached

(003Fh), the address counter will roll over to the lowest

address (0000h), allowing the entire Security register to

be read in one continuous read cycle regardless of the

starting address.

FIGURE 9-1:

READ SECURITY REGISTER (

RDEX) SEQUENCE

TABLE 9-1:

SECURITY REGISTER ORGANIZATION

Security Register Byte Number

...

Factory-Programmed (Read-Only)

0-15: Device Serial Number

16-31: Reserved for Future Use

User-Programmable (Lockable)

Note:

Address bits A15 through A6 are “don't

care” bits, except for A10, which must be

a logic ‘0’.

10 0 0 00 11

A A A

RDEX Opcode (83h)

XX XX X 0

Data Byte 1

MSb

High-Impedance

Note 1:

Address bit A10 must be logic ‘0’ to read the Security register.

D5 D4 D3 D2 D1 D0

D7 D6

SCK

234

567

9 10 11 12

32 33

Address Bits A15-A0(1)

10 0 0 00 11

A A A

XX XX X 0

Data Byte 1

High-Impedance

D5 D4 D3 D2 D1 D0

D7 D6

Address Bits A15-A0(1)

25CS160-H/ST Datasheet(PDF) 26 Page - Microchip Technology

25CS160-H/ST Datasheet(HTML) 26 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL