25CS160-HSLASHST datasheet(17/53 Pages) MICROCHIP

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Preliminary

DS20007008B-page 17

25CS160

5.0

WRITE ENABLE AND DISABLE

5.1

Write Enable Instruction (WREN)

The Write Enable Latch (WEL) bit of the STATUS

WRITE, WREX, or LOCK instruction. The WEL bit is set

to a logic ‘1’ by sending a WREN (06h) instruction to the

25CS160. First, the CS pin is driven low to select the

device, and then a 06h instruction is clocked in on the

SI pin. After that, the CS pin is driven high. The WEL bit

will be immediately updated in the STATUS register to

a logic ‘1’.

The WEL bit will be reset to a logic ‘0’ in the following

circumstances:

• Upon power-up, as the power-on default condition

is in the Write Disable state (Section 1.2.2

“Device Factory Default Condition”)

• Upon the successful completion of any write

sequence (WRITE, WRSR, WREX)

• Upon execution of a Write Disable (WRDI)

instruction (Section 5.2 “Write Disable (WRDI)

Instruction”)

• Upon execution of a Software Device Reset

(SRST) instruction

FIGURE 5-1:

WRITE ENABLE (

WREN) INSTRUCTION

5.2

Write Disable (WRDI) Instruction

To protect the device against inadvertent write

sequences, the Write Disable (04h) instruction disables

all programming modes by setting the WEL bit to a

logic ‘0’. The WRDI instruction is independent of the

WP pin state.

FIGURE 5-2:

WRITE DISABLE (

WRDI) INSTRUCTION

SCK

456

High-Impedance

WREN Opcode (06h)

000

MSb

SCK

567

High-Impedance

WRDI Opcode (04h)

000

MSb

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