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CY7B995ACT Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY7B995ACT
Description  2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer
PDF  13 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7B995ACT Datasheet(HTML) 5 Page - Cypress Semiconductor

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RoboClock®, CY7B995
Document #: 38-07337 Rev. *D
Page 5 of 13
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in Table 10 on page 5. Refer to the AC Timing Definitions section
for a description of input-to-output and output-to-output phase
relationships.
Table 10. PE/HD Settings
The CY7B995 features split power supply buses for Banks 1 and
2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V
and 2.5V output signals from one device. The core power supply
(VDD) must be set at a level that is equal to or higher than any of
the output power supplies.
Table 11. Power Supply Constraints
Governing Agencies
The following agencies provide specifications that apply to the
CY7B995. The agency name and relevant specification is listed
below.
Table 12. Governing Agencies and Specifications
PE/HD
Synchronization
Output Drive Strength[9]
L
Negative
Low Drive
M
Positive
High Drive
H
Positive
Low Drive
VDD
VDDQ1
[10]
VDDQ3
[10]
VDDQ4
[10]
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
2.5V
2.5V
2.5V
2.5V
Agency Name
Specification
JEDEC
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
IEEE
1596.3 (Jiter Specs)
UL-194_V0
94 (Moisture Grading)
MIL
883E Method 1012.1
(Therma Theta JC)
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Operating Voltage
Functional @ 2.5V ± 5%
2.25
2.75
V
VDD
Operating Voltage
Functional @ 3.3V ± 10%
2.97
3.63
V
VIN(MIN)
Input Voltage
Relative to VSS
VSS – 0.3
–
V
VIN(MAX)
Input Voltage
Relative to VDD
–
VDD + 0.3
V
VREF(MAX)
Reference Input Voltage
VDD = 3.3V
5.5
V
VREF(MAX)
Reference Input Voltage
VDD = 2.5V
4.6
V
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
–
155
°C
ØJC
Dissipation, Junction to Case
Mil-Spec 883E Method 1012.1
–
42
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
74
°C/W
ESDHBM
ESD Protection (Human Body Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
@1/8 in.
V–0
MSL
Moisture Sensitivity Level
1
FIT
Failure in Time
Manufacturing Testing
10
ppm
Notes
7. LL disables outputs if TEST = MID and sOE# = HIGH.
8. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID, sOE# disables them LOW when PE/HD = LOW.
9. Please refer to “DC Parameters” section for IOH/IOL specifications.
10. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V
and VDDQ4 = 2.5V.
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