9 / 13 page
RoboClock®, CY7B995
Document #: 38-07337 Rev. *D
Page 9 of 13
AC Timing Definitions
Figure 2. Timing Definition
With PE HIGH (LOW), the REF rising (falling) edges are aligned
to the FB rising (falling) edges. Also, when PE is HIGH (LOW),
all divided outputs’ rising (falling) edges are aligned to the rising
(falling)
edges
of
the
undivided,
non-inverted
outputs.
Regardless of PE setting, divide-by-4 outputs’, rising edges align
to the divide-by-2 outputs’ rising edges.
In cases where a non-divided output is connected to the FB input
pin, the divided output rising edges can be either 0 or 180
degrees phase aligned to the REF input rising edges (as set
randomly at power-up). If the divided outputs are required as
rising-edge (falling-edge) aligned to the REF input’s rising
(falling) edge, set the PE pin HIGH (LOW) and connect the
lowest frequency divided output to the FB input pin. This setup
provides a consistent input-output and output-output phase
relationship.
t
REF
t
0DCV
t
0DCV
t
PD
t
CCJ1-12
t
SKEWPR
t
SKEW0,1
t
SKEWPR
t
SKEW0,1
t
SKEW1
t
SKEW1
t
SKEW3
t
SKEW3
t
SKEW3
t
SKEW1,3,4
t
SKEW1,3,4
t
PWH
t
PWL
REF
FB
Q
OTHER Q
INVERTED Q
DIVIDE BY 2 OUTPUT
DIVIDE BY 4 OUTPUT
[+] Feedback
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
