L6711 datasheet(29/50 Pages) STMICROELECTRONICS

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L6711

Dynamic VID transitions

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11.1

VID_SEL = OPEN.

Selecting the VRD10.x DAC, the device checks for VID code modifications on the rising

edge of a clock that is three times the switching frequency of each phase and waits for a

confirmation on the following falling edge. Once the new code is stable, on the next rising

edge, the reference starts stepping up or down in LSB increments (12.5mV) every clock

cycle (still 3·FSW) until the new VID code is reached. During the transition, VID code

changes are ignored; the device re-starts monitoring VID after the transition has finished on

the next rising edge available.

Warning:

if the new VID code is more than 1 LSB higher than the

previous, the device will execute the transition stepping the

reference with a frequency equal to 3·FSW until the new code

has reached: for this reason it is recommended to carefully

control the VID change rate in order to carefully control the

slope of the output voltage variation.

Warning:

DVID sample and hold clock depends on the switching

frequency FSW. To correctly perform DVID transition so

following the VID change rate, it is required to have at least 2

complete cycles of the FDVID clock between every VID

transition. If the VID update-rate is, for example, 5

µs, the

minimum operating frequency results to be FSW > 133kHz.

Figure 14.

Dynamic VID Transition, Hammer DAC

4 Step VID Transition - Hammer DAC

VID [0,5]

Int. Reference

Vout

Tsw

VID Clock

L6711 Datasheet(PDF) 29 Page - STMicroelectronics