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db12348e_V3.11_preliminary_2017-07-06

Page 24 of 41

AS89010

V3.11

6.2.3 Options Register - OPTREG

This register sets additional options of the device which can enhance performance according to the given

application.

Table 12: OPTREG register - Address 08h

OPTREG

NAME

VALUE

[b]

AFFECTED CONFIGURATION

bit 7 to 2

--

00000024 must be used

Offset Value

(conversion output for zero input current)

0024

0dec (disable offset generation)

01

15dec (in SYND Mode: TINT·fCLK /27)

10

31dec (in SYND Mode: TINT·fCLK /211)

11

63dec (in SYND Mode: TINT·fCLK /215)

The ZERO enables an internal offset generation to the input current and conversion result, too. It makes

the device able to measure very low e.g. zero input current even in presence of the negative leakage

current, which would normally lead to an underflow.

6.2.4 Register – BREAK

Table 13: BREAK register - Address 09h

BREAK

NAME

VALUE

[dec]

AFFECTED CONFIGURATION

bit 7 to 0

BREAK 1 - 255 break between measurements

(only in CONT measurement mode)

CONT: BREAK / fCLK typically; 5 µs to 1021 µs

in steps (1 µs + 4 µs * break time)

CMD: BREAK / fCLK typically; 1 µs to 255 µs in 1 µs steps

This register takes effect only in CONT and CMD measurement mode. In the CONT Mode it defines the

break between two consequent measurements25. In the CMD Mode it defines the delay between a command

for measurement start and the actually start of the measurement. This register gives a chance to the device

to perform the measurement in the time when no disturbances occur during the I²C communication. Value

of ‘0’ cannot be written and will be ignored. The default value is 20h.

24 Default after power-on-reset and state change from measurement to configuration.

25 In case of an active I²C communication the AS89010 should not be active in converting. Therefore the break time between two

measurements should be a minimum of >300 µs. (25 µs / Byte * (2 x 4 signal bytes+ 2 x control byte) * 1.25 clock tolerance).