AS89010 datasheet(16/43 Pages) AMSOSRAM

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db12348e_V3.11_preliminary_2017-07-06

Page 14 of 41

AS89010

V3.11

content of register CREGL: R and T bits (T). Their values determine directly the sensitivity e.g. LSB and

full-scale range (FSR) current of A/D conversion. One overview of the possible configurations is shown in

Table 5.

Table 5: Programmable FSR and LSB current (CONT, CMD, SYNS Mode)

T [b]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

NCLK

1024

2048

4096

8129

16384

32768

65536 131072 262144

524288

1048576

Resolution

[bit]

R [b]

IFSR [nA]

000

2.5

1.25

001

010

320

160

011

1280

640

320

160

1XX

5120

2560

1280

640

320

R [b]

LSB [pA]

000

19.53

9.77

4.88

2.44

1.22

0.61

0.31

0.15

0.08

0.04

0.02

001

78.13 39.06 19.53

9.77

4.88

2.44

1.22

0.61

0.31

0.15

0.08

010

312.5 156.25 78.12 39.06

19.53

9.77

4.88

2.44

1.22

0.61

0.31

011

1250

625

312.5 156.25 78.13

39.06 19.53

9.77

4.88

2.44

1.22

1XX

5000

2500

1250

625

312.5 156.25 78.13 39.06

19.53

9.77

4.88

The maximum value of conversion result in the SYND Mode depends on the external integration time

duration. This maximum achievable count is equal to OUTINT and differs from the full-scale count

achievable in CMD, CONT and SYNS Mode. The value of T defines the number of clock counts during the

integration time. It defines the integration e.g. conversion time duration and maximum of resolution of the

A/D conversion. This is valid for the CONT, CMD and SYNS Mode.

In the SYND Mode the value of T has no meaning, integration time duration is externally defined. The

values of T higher than 0110b internally lead to A/D conversion with a higher resolution up to 20 bit. But

only the 16 most significant bits will be further processed and stored. As only the lower part of results is

evaluated, the FSR is lower for internal resolution higher than 16 bit. The value of R defines the A/D

converter reference current (see T). In combination with the values of T or the integration time duration it

also defines the full-scale range current and thus the sensitivity of the A/D conversion.

During a conversion an overflow of input integrator of the A/D converter must be avoided. The maximum

input current must not exceed the double value of reference current for the maximum of one clock duration,

otherwise integrator overflow can occur and conversion result would be incorrect:

IREF

MAX



 2

(4)

MAX

: Peak Input Current

For more details and necessary steps to find the optimal parameters for amplifying please see our notices

in the application note “AppNote specifying the optimal gain parameters for AS89010.pdf”14.

14 Please contact our sales team - see page 40

bit 3 to 0 of CREGL

bit 6 to 4 of CREGL

IFSR: full-scale range current

LSB:

last significant bit

Resolution: internal A/D resolution

NCLK = TINT . fCLK

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