AS89010 datasheet(11/43 Pages) AMSOSRAM

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db12348e_V3.11_preliminary_2017-07-06

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AS89010

V3.11

5 DESCRIPTION OF FUNCTION

The AS89010 performs current to digital conversion by four parallel A/D converters. The sensitivity, start

and stop of conversion are user defined and should be adapted to the application of interest. Upon the end

of each conversion, the digital equivalents of the input currents are stored in the output register (OUT0 to

OUT3). Pin READY stays at low logic level all the time during the conversion. Rising edge and following high

logic level of READY signalizes the end of conversion.

5.1 Measurement Modes

There are four available modes how the measurement can be performed. According to the assignment of

However, it is always recommended regardless of the mode, to transfer no data via I²C during the

measurement process. It is suggested to use the measurement-free time cycles for data transfer via I²C.

5.1.1 Continuous Measurement Mode (CONT Mode)

The A/D conversion will be performed sequentially. The first conversion starts with setting the SS bit in

OSR register. If the Standby was active, the device deactivates it and initializes the continuous

measurement. Measurement can only be stopped by resetting the SS bit. The conversion time (integration

time TINT) is determined by the full-scale of the register CREGL:T (T). The rising edge of READY signalizes

the end of each conversion. It is recommended to read output data during the break time between two

consequent conversions in order to not disturb the integration operation. This break time can be configured

in 4 µs steps up to 1,021 µs (see Table 13). The break time should be configured long enough to prevent

overlapping of data fetch activity with the measurement. For further details see also Figure 21.

Figure 3: CONT Mode timing with short break time

data

fetch

idle or

standby

data

fetch

data

fetch

data

fetch

idle or

standby

conversion

READY

OUT0..OUT3

TINT

STATE

I²C

activity

break time

start (SS

←’1')

end (SS

←’0')

Figure 4: CONT Mode timing with long enough break time between subsequent conversions

start (SS

←’1')

data

fetch

data

fetch

conversion

READY

OUT0..OUT3

TINT

STATE

I²C

activity

break time

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