AS89010 datasheet(27/43 Pages) AMSOSRAM

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db12348e_V3.11_preliminary_2017-07-06

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AS89010

V3.11

6.2.5 Register – EDGES

This register takes effect only in SYND measurement mode. It defines a number of falling edges at SYN

input at the end of the integration. Value of ‘0’ cannot be written and will be ignored. The default value is

01h.

Table 14: EDGES - Address 0Ah

EDGES

NAME

VALUE [dec]

AFFECTED CONFIGURATION

bit 7 to 0

EDGES

1 - 255

number of SYN falling edges

6.3 Output Register Bank

The results of the conversion are stored into four 16 bit registers, addressing is shown in the Table 15.

measurement mode the externally controlled conversion time can be internally measured in time units of

the system clock (see chapter 5.5). This time measurement is enabled by setting the ENTM bit of CREGH

depends on the internal clock frequency. Because clock frequency can differ from one AS89010 to another

the value of OUTINT can be used to normalize the conversion results delivered in output registers OUT0 to

OUT3 (see chapter 5.4). Additionally, the value of OUTINT can be used to estimate the current level of

magnitude. At the end of each conversion e.g. measurement, the value of all available register will be

refreshed. If a measurement finishes during the readout cycle of the output register, then the refresh of

these new values is delayed until the read cycle is completed.

Table 15: Output register addressing space

ADDRESS

[hex]

ACCESS26

NAME

NO. OF

BITS

DESCRIPTION

OUT0

output register,

conversion result for current at IN0

OUT1

output register,

conversion result for current at IN1

OUT2

output register,

conversion result for current at IN2

OUT3

output register,

conversion result for current at IN3

OUTINT27

result of integration time measurement

(only 20 bits are valid)

The register OUTINT is only needed in the SYND mode. It measures the time of the measurement in units

of the internal clock. For all other modes this time is internally defined by the programmed value CREGL:T.

So use equation (1) with the value N_CLK from Table 5 or Table 10.

For the SYND mode use equation (3) with the OUTINT value from the result register 4 to calculate the input

current. Only with CREGL:ENTM=1 gives valid results. This means CREGH:ENTM=0 will produce wrong data

here. Other modes than SYND also gives wrong values. Unfortunately there are some values there in this

cases. For the Reading of the results I suggest to address the first result register (OUT0 @ internal address

0) and then to read 8 bytes with the auto increment of the internal address.

26 ro – Read-only

27 This register is only valid if the integration time measurement has been chosen (ENTM=1b), but in SYND Mode only.

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