R5F526TBAGFM datasheet(90/142 Pages) RENESAS

90 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 90 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

Note 1. tPcyc refers to the period of PCLKB.

Note 2. Cb is the total capacitance of the bus lines.

Figure 2.38

Simple IIC Bus Interface Input/Output Timing

Table 2.32

Simple IIC Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.*1

Unit

Test Conditions

Simple IIC

(Standard-mode)

SSDA input rise time

tSr

—

1000

Figure 2.38

SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal time

tSP

04 × tPcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*2

—

400

Simple IIC

(Fast-mode)

SSDA input rise time

tSr

—

300

SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal time

tSP

04 × tPcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*2

—

400

SSDAn

(n = 1, 5, 6, and 12)

SSCLn

(n = 1, 5, 6, and 12)

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions

VIH = 0.7 × VCC, VIL = 0.3 × VCC

VOL = 0.6 V, IOL = 6 mA

VOL = 0.4 V, IOL = 3 mA

Sr*1

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition

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