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R5F526TBAGFM Datasheet(PDF) 100 Page - Renesas Technology Corp |
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R5F526TBAGFM Datasheet(HTML) 100 Page - Renesas Technology Corp |
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100 / 142 page ![]() R01DS0407EJ0120 Rev.1.20 Page 100 of 142 Oct 31, 2024 RX26T Group 2. Electrical Characteristics 2.4.5.11 RSPI Note 1. tPAcyc: PCLKA cycle Table 2.37 RSPI Timing Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max.*1 Unit*1 Test Conditions RSPI RSPCK clock cycle Master tSPcyc 2— tPAcyc Figure 2.52 Slave 4 — RSPCK clock high pulse width Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 —ns Slave 0.4 0.6 tSPcyc RSPCK clock low pulse width Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 —ns Slave 0.4 0.6 tSPcyc RSPCK clock rise/fall time Output tSPCKr, tSPCKf —5 ns Input — 1 µs Data input setup time Master tSU 6 — ns VCC ≥ 4.5 V Figure 2.53 to Figure 2.58 11 — VCC < 4.5 V Slave 8.3 — Figure 2.53 to Figure 2.58 Data input hold time PCLKA division ratio set to 1/2 tHF 0— ns PCLKA division ratio set to a value other than 1/2 tH tPAcyc — Slave 8.3 — SSL setup time Master tLEAD 18 tSPcyc Slave 4 — tPAcyc SSL hold time Master tLAG 18 tSPcyc Slave 4 — tPAcyc Data output delay time Master tOD — 6.3 ns VCC ≥ 4.5 V Figure 2.53 to Figure 2.58 — 11.3 VCC < 4.5 V Slave — 28 VCC ≥ 4.5 V — 33 VCC < 4.5 V Data output hold time Master tOH 0 — ns Figure 2.53 to Figure 2.58 Slave 0 — Successive transmission delay time Master tTD tSPcyc + 2 × tPAcyc 8 × tSPcyc + 2 × tPAcyc ns Slave 4 × tPAcyc — MOSI and MISO rise/fall time Output tDr, tDf —5 ns Input — 1 µs SSL rise/fall time Output tSSLr, tSSLf —5 ns Input — 1 µs Slave access time tSA — 28 ns VCC ≥ 4.5 V Figure 2.57, Figure 2.58 — 33 VCC < 4.5 V Slave output release time tREL — 28 ns VCC ≥ 4.5 V — 33 VCC < 4.5 V |
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