| Electronic Components Datasheet Search |
|
R5F526TBAGFM Datasheet(PDF) 105 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F526TBAGFM Datasheet(HTML) 105 Page - Renesas Technology Corp |
|
105 / 142 page ![]() R01DS0407EJ0120 Rev.1.20 Page 105 of 142 Oct 31, 2024 RX26T Group 2. Electrical Characteristics 2.4.5.12 RSPIA Note 1. tPAcyc: PCLKA cycle Table 2.38 RSPIA Timing Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V, VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 15 pF, High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max.*1 Unit*1 Test Conditions RSPI RSPCK clock cycle Master tSPcyc 2— tPAcyc Figure 2.59 Slave 2 — RSPCK clock high pulse width Master tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 —ns Slave 0.4 0.6 tSPcyc RSPCK clock low pulse width Master tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 – 3 —ns Slave 0.4 0.6 tSPcyc RSPCK clock rise/fall time Output tSPCKr, tSPCKf —5 ns Input — 1 µs Data input setup time Master tSU 0— ns VCC ≥ 4.5 V Figure 2.60 to Figure 2.66 2.5 — VCC < 4.5 V Slave 2.5 — Data input hold time Master tH 7— ns Slave 2.5 — SSL setup time Master tLEAD 18 tSPcyc Slave 6 — tPAcyc SSL hold time Master tLAG 18 tSPcyc Slave 6 — tPAcyc Data output delay time Master tOD —4.5 ns VCC ≥ 4.5 V — 5.5 VCC < 4.5 V Slave — 14 VCC ≥ 4.5 V — 18 VCC < 4.5 V Data output hold time Master tOH 0— ns Slave 0 — Successive transmission delay time Master tTD tSPcyc + 2 × tPAcyc 8 × tSPcyc + 2 × tPAcyc ns Slave tSPcyc — MOSI and MISO rise/fall time Output tDr, tDf —5 ns Input — 1 µs SSL rise/fall time Output tSSLr, tSSLf —5 ns Input — 1 µs Slave access time tSA — 20 ns Figure 2.63, Figure 2.64 Slave output release time tREL —20 ns TI SSP SS input setup time Slave tTISS 4.5 — ns Figure 2.65, Figure 2.66 TI SSP SS input hold time Slave tTISH 2.5 — ns TI SSP next-access delay time Slave tTIND 2 × tPAcyc + SLNDL × tPAcyc —ns TI SSP SS output delay time Master tTISSOD — 7 ns Figure 2.62 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |