R5F5671CDDLE datasheet(5/179 Pages) RENESAS

5 / 179 page

RX671 Group

1. Overview

R01DS0373EJ0120 Rev.1.20

Page 5 of 179

Sep 30, 2024

I/O ports

Programmable I/O ports

 I/O ports for the 145-pin TFLGA (0.65-mm pitch)

I/O pins: 111

Input pin: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 20

 I/O ports for the 145-pin TFLGA (0.50-mm pitch) and 144-pin LFQFP

I/O pins: 113

Input pin: 1

Pull-up resistors: 113

Open-drain outputs: 113

5-V tolerance: 20

 I/O ports for the 100-pin TFLGA and 100-pin LFQFP

I/O pins: 80

Input pin: 1

Pull-up resistors: 80

Open-drain outputs: 80

5-V tolerance: 18

 I/O ports for the 64-pin TFBGA

I/O pins: 43

Input pin: 1

Pull-up resistors: 43

Open-drain outputs: 43

5-V tolerance: 8

 I/O ports for the 64-pin LFQFP

I/O pins: 44

Input pin: 1

Pull-up resistors: 44

Open-drain outputs: 44

5-V tolerance: 8

 I/O ports for the 48-pin HWQFN

I/O pins: 33

Input pin: 1

Pull-up resistors: 33

Open-drain outputs: 33

5-V tolerance: 6

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 99 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

Timers

16-bit timer pulse unit

(TPUa)

 (16 bits × 6 channels) × 1 unit

 Maximum of 16 pulse-input/output possible

 Select from among seven or eight counter-input clock signals for each channel

 Input capture/output compare function

 Output of PWM waveforms in up to 15 phases in PWM mode

 Support for buffered operation, phase-counting mode (two phase encoder input) and

cascade-connected operation (32 bits × 2 channels) depending on the channel.

 PPG output trigger can be generated

 Capable of generating conversion start triggers for the A/D converters

 Digital filtering of signals from the input capture pins

 Event linking by the ELC

8-bit timers (TMRb)

 (8 bits × 2 channels) × 2 units

 Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,

PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal

 Capable of output of pulse trains with desired duty cycles or of PWM signals

 The 2 channels of each unit can be cascaded to create a 16-bit timer

 Generation of triggers for A/D converter conversion

 Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12

 Capable of generating operating clock for the remote control signal receiver (REMC)

 Event linking by the ELC

Table 1.1

Outline of Specifications (4/10)

Classification

Module/Function

Description

R5F5671CDDLE Datasheet(PDF) 5 Page - Renesas Technology Corp

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