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MSC8113 Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc |
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MSC8113 Datasheet(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 44 page ![]() MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0 Electrical Characteristics Freescale Semiconductor 22 Table 14. AC Timing for SIU Inputs No. Characteristic Ref = CLKIN at 1.1 V and 100/133 MHz Units 10 Hold time for all signals after the 50% level of the REFCLK rising edge 0.5 ns 11a ARTRY/ABB set-up time before the 50% level of the REFCLK rising edge 3.1 ns 11b DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge 3.6 ns 11c AACK set-up time before the 50% level of the REFCLK rising edge 3.0 ns 11d TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode 3.5 4.4 ns ns 12 Data bus set-up time before REFCLK rising edge in Normal mode • Data-pipeline mode • Non-pipeline mode 1.9 4.2 ns ns 131 Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes • Data-pipeline mode • Non-pipeline mode 2.0 8.2 ns ns 141 DP set-up time before the 50% level of the REFCLK rising edge • Data-pipeline mode • Non-pipeline mode 2.0 7.9 ns ns 15a TS and Address bus set-up time before the 50% level of the REFCLK rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • No extra cycle mode (SIUBCR[EXDD] = 1) 4.2 5.5 ns ns 15b Address attributes: TT/TBST/TSZ/GBL set-up time before the 50% level of the REFCLK rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • No extra cycle mode (SIUBCR[EXDD] = 1) 3.7 4.8 ns ns 16 PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge 3.7 ns 17 IRQx setup time before the 50% level; of the REFCLK rising edge3 4.0 ns 18 IRQx minimum pulse width3 6.0 + TREFCLK ns Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings. 2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge. 3. Guaranteed by design. |
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