MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freescale Semiconductor

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If there is an external bus master (BCR[EBM] = 1):

functionality.

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modes, they must be pulled up.

Note:

The MSC8113 does not support DLL-enabled mode. For the following two clock schemes, ensure that the DLL is

disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).

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If no system synchronization is required (for example, the design does not use SDRAM), you can use any of the

available clock modes.

between the clock buffer to the MSC8113 and the SDRAM is equal (that is, has a skew less than 100 ps).

— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.

Note:

See the Clock chapter in the MSC8113 Reference Manual for details.

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should be pulled up.

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be pulled up.

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externally to any signal line.

Note:

For details on configuration, see the MSC8113 User’s Guide and MSC8113 Reference Manual. For additional

information, refer to the MSC8113 Design Checklist (ANxxxx).

3.4

External SDRAM Selection

The external bus speed implemented in a system determines the speed of the SDRAM used on that bus. However, because of

differences in timing characteristics among various SDRAM manufacturers, you may have use a faster speed rated SDRAM to

assure efficient data transfer across the bus. For example, for 133 MHz operation, you may have to use 133 or 166 MHz

SDRAM. Always perform a detailed timing analysis using the MSC8113 bus timing values and the manufacturer specifications

for the SDRAM to ensure correct operation within your system design. The output delay listed in SDRAM specifications is

usually given for a load of 30 pF. Scale the number to your specific board load using the typical scaling number provided by

the SDRAM manufacturer.