MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freescale Semiconductor

16

2.5

AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When

systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF

load, except where noted otherwise, and a 50

Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down

to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.

When calculating overall loading, also consider additional RC delay.

2.5.1

Output Buffer Impedances

2.5.2

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3

describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the

following guidelines when starting up an MSC8113 device:

•

PORESET

•

•

CLKIN

deassertion to guarantee correct device operation (see Figure 6 and Figure 7).

•

CLKIN

Table 6. Output Buffer Impedances

Output Buffers

Typical Impedance (

Ω)

System bus

50

Memory controller

50

Parallel I/O

50

Note:

These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.

Time

o.5 V

3.3 V

1.1 V

PORESET/TRST Asserted

CLKIN Starts Toggling

PORESET/TRST Deasserted

1

2.2 V