MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

36

2.5.12

EE Signals

2.5.13

JTAG Signals

Table 29. EE Pin Timing

Number

Characteristics

Type

Min

65

EE0 (input)

Asynchronous

4 core clock periods

66

EE1 (output)

Synchronous to Core clock

1 core clock period

Notes:

1.

The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.

2.

Refer to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 27. EE Pin Timing

Table 30. JTAG Timing

No.

Characteristics

All

frequencies

Unit

Min

Max

700

TCK frequency of operation (1/(T

4); maximum 25 MHz)

0.0

25

MHz

701

TCK cycle time

40.0

—

ns

702

•High

•Low

20.0

16.0

—

—

ns

ns

703

TCK rise and fall times

0.0

3.0

ns

704

Boundary scan input data set-up time

5.0

—

ns

705

Boundary scan input data hold time

20.0

—

ns

706

TCK low to output data valid

0.0

30.0

ns

707

TCK low to output high impedance

0.0

30.0

ns

708

TMS, TDI data set-up time

5.0

—

ns

709

TMS, TDI data hold time

20.0

—

ns

710

TCK low to TDO data valid

0.0

20.0

ns

711

TCK low to TDO high impedance

0.0

20.0

ns

712

TRST assert time

100.0

—

ns

713

TRST set-up time to TCK low

30.0

—

ns

Note:

All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

EE1 out

EE0 in

65

66