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DS72011RB120FPV Datasheet(PDF) 337 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 337 Page - Renesas Technology Corp |
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337 / 1196 page  Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 309 of 1164 REJ09B0321-0200 11.3.2 DMA Current Destination Address Register (DMCDADR) DMCDADR is a register used to specify the start address of the transfer destination. The value in this register is transferred to the working destination-address register at the start of DMA transfer. The default behavior is for the contents of the working destination-address register to be returned on completion of each single operand transfer. However, the contents of the working destination- address register are not returned in two cases: when the rotate setting (SAMOD = 011) is made for the destination address and when the destination-address reload function is enabled. In the latter case, the contents of the DMA reload destination address register (DMRDADRn) are returned to this register on completion of DMA transfer. This register must be set before transfer is initiated, regardless of whether the reload function is enabled or disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W CDA CDA Bit Bit Name Initial Value R/W Description 31 to 0 CDA Undefined R/W Holds destination address bits A31 to A0 Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. • When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". • When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). 2. Only write to this register when single operand transfer is not in process on the corresponding channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT) or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when both conditions are not satisfied. |
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