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DS72011RB120FPV Datasheet(PDF) 341 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 341 Page - Renesas Technology Corp |
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341 / 1196 page ![]() Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 313 of 1164 REJ09B0321-0200 11.3.6 DMA Reload Byte Count Register (DMRBCT) DMRBCT is a register used to set the number for reloading to the DMA current byte count register (DMCBCTn). To enable reloading, set the DMA byte count reload function enable bit (BRLOD) in the DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current byte count register (DMCBTn) and DMA reload byte count address register (DMRBCTn). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 000000 — R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — — — — — — — — — — — — — — — — — — ——————— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —————— RBC RBC Bit Bit Name Initial Value R/W Description 31 to 26 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 25 to 0 RBC Undefined R/W Number of bytes to be DMA-transferred after reloading Note: Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. • When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". • When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). |
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