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DS72011RB120FPV Datasheet(PDF) 340 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 340 Page - Renesas Technology Corp |
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340 / 1196 page  Section 11 Direct Memory Access Controller (DMAC) Rev. 2.00 Sep. 07, 2007 Page 312 of 1164 REJ09B0321-0200 11.3.5 DMA Reload Destination Address Register (DMRDADR) DMRDADR is a register used to set an address for reloading to the DMA current destination address register (DMCDADRn). To enable reloading, set the DMA destination address reload function enable bit (DRLOD) in DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current destination address register (DMCDADRn) and DMA reload destination address register (DMRDADRn). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RDA RDA Bit Bit Name Initial Value R/W Description 31 to 0 RDA Undefined R/W Holds destination address bits A31 to A0 for reloading Note: Set this register so that DMA transfer is performed within the correctly aligned address boundaries for the transfer sizes listed below. • When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0". • When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0). |
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