DS72011RB120FPV datasheet(346/1196 Pages) RENESAS

Part #	DS72011RB120FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1196 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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346 / 1196 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 318 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

DACT

Undefined R/W

DMA Active Signal Output for Destination

This bit is used to control the output of the DMA-active

signal (DACT) for the destination corresponding to the

request source setting in the DCTG bits.

When this bit is set to "0", output of the DACT signal is

disabled and fixed high unless the level changes

because of the SACT bit setting.

When this bit is set to "1", output of the DACT signal is

valid ("L") from the next cycle after the start of the

DMAC read cycle.

However, while output of the DACT signal is enabled

when the DMA request source selection (DCTG) bits

are set for software triggering, a valid DACT signal

cannot be output when the requesting source is an on-

chip peripheral circuit (DCTG), regardless of the

setting of the DACT bit.

0: Stops output of the DMA-active signal for the

destination

1: Selects output of the DMA-active signal for the

destination during write access

DS72011RB120FPV Datasheet(PDF) 346 Page - Renesas Technology Corp