DS72011RB120FPV datasheet(348/1196 Pages) RENESAS

348 / 1196 page

Section 11 Direct Memory Access Controller (DMAC)

Rev. 2.00 Sep. 07, 2007 Page 320 of 1164

REJ09B0321-0200

Table 11.3 shows the DMA source/destination address registers. For details on the rotation address

"indexing" mode, see section 11.11, Rotate Function. Note that when performing pipelined

transfer to or from external devices and modules that support burst access, make sure to set the

direction bits to select address incrementation ("001") or rotation ("011").

Table 11.3

Increment/Decrement for DMA Source/Destination Address Registers

Address Indexing Mode

SAMOD or DAMOD

Transfer data size

selection bits

SZSEL

"000"

(fixed)

"001"

(plus direction)

"010"

(minus direction)

"011"

(rotation)

"000" (8 bits)

±0

−1

"001" (16 bits)

±0

−2

"010" (32 bits)

±0

−4

11.3.8

DMA Control Register A (DMCNTA)

DMCNTA handles the selections of the transfer mode and the condition of transfer, control of

reload functions, and selection of DMA sources.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

R/W

RRRRRR

R/W

0000000000000000

R/W

—

MDSEL[1:0]

—

DSEL[1:0]

—

STRG[1:0]

—————

BRLOD SRLOD DRLOD

—

DCTG[5:0]

Bit

Bit Name

Initial

Value

R/W

Description

31, 30



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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