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DS72011RB120FPV Datasheet(PDF) 182 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 182 Page - Renesas Technology Corp |
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182 / 1196 page  Section 6 Interrupt Controller (INTC) Rev. 2.00 Sep. 07, 2007 Page 154 of 1164 REJ09B0321-0200 6.8 Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration. General registers Bank control register Bank number register Bank control registers (interrupt controller) Banked register Vector table address offset Note: Interrupt generated (save) RESBANK instruction (restore) Registers Register banks Bank 0 Bank 1 .... Bank 14 R0 R1 : : R14 R15 SR GBR VBR TBR MACH MACL PR PC Control registers System registers R0 R1 : : R14 GBR IVO VTO: IBCR IBNR MACH MACL PR : Figure 6.10 Overview of Register Bank Configuration |
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