DS72011RB120FPV datasheet(203/1196 Pages) RENESAS

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Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 175 of 1164

REJ09B0321-0200

7.4.3

Break on Data Access Cycle

1. If the C bus is specified as a break condition for data access break, condition comparison is

performed for the logical addresses (and data) accessed by the executed instructions, and a

break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition

comparison is performed for the addresses (and data) of the data access cycles on the bus

specified by the I bus select bits, and a break occurs if the condition is satisfied. For details on

the CPU bus cycles issued on the I bus, see 6 in section 7.4.1, Flow of the User Break

Operation.

2. The relationship between the data access cycle address and the comparison condition for each

operand size is listed in table 7.3.

Table 7.3

Data Access Cycle Addresses and Operand Size Comparison Conditions

Access Size

Address Compared

Longword

Compares break address register bits 31 to 2 to address bus bits 31 to 2

Word

Compares break address register bits 31 to 1 to address bus bits 31 to 1

Byte

Compares break address register bits 31 to 0 to address bus bits 31 to 0

This means that when address H'00001003 is set in the break address register (BAR), for

example, the bus cycle in which the break condition is satisfied is as follows (where other

conditions are met).

Longword access at H'00001000

Word access at H'00001002

Byte access at H'00001003

3. When the data value is included in the break conditions:

When the data value is included in the break conditions, either longword, word, or byte is

specified as the operand size in the break bus cycle register (BBR). When data values are

included in break conditions, a break is generated when the address conditions and data

conditions both match. To specify byte data for this case, set the same data in the four bytes at

bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 of the break data register (BDR) and break data mask

31 to 16 and 15 to 0.

4. Access by a PREF instruction is handled as read access in longword units without access data.

Therefore, if including the value of the data bus when a PREF instruction is specified as a

break condition, a break will not occur.

5. If the data access cycle is selected, the instruction at which the break will occur cannot be

determined.

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