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DS72011RB120FPV Datasheet(PDF) 234 Page - Renesas Technology Corp |
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DS72011RB120FPV Datasheet(HTML) 234 Page - Renesas Technology Corp |
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234 / 1196 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 206 of 1164 REJ09B0321-0200 Internal Address Space Memory to be Connected Cache H'40000000 to H'4FFFFFFF CS6 Normal space Cache- disabled H'50000000 to H'E7FFFFFF Other Reserved area* — H'E8000000 to H'EFFFFFFF Other On-chip peripheral modules, reserved area* — H'F0000000 to H'FF3FFFFF Other Cache address array space, reserved area* — H'FF400000 to H'FFF7FFFF Other On-chip peripheral modules, reserved area* — H'FFF80000 to H'FFFBFFFF Other On-chip RAM, reserved area* — H'FFFC0000 to H'FFFFFFFF Other On-chip peripheral modules, reserved area* — Note: * For the on-chip RAM space, access the addresses shown in section 24, On-Chip RAM. For the on-chip peripheral module space, access the addresses shown in section 28, List of Registers. Do not access addresses which are not described in these sections. Otherwise, correct operation cannot be guaranteed. 9.3.2 Data Bus Width and Pin Function Setting for Individual Areas In this LSI the data bus width of area 0 can be set to 8, 16, or 32 bits through external pins during a power-on reset. The data bus widths of areas 1 to 6 can be modified through register settings during program execution. Note that the selectable data bus widths may be limited depending on the connected memory type. After a power-on reset, the LSI starts execution of the program stored in the external memory allocated in area 0. For details on pin function settings, see section 23, Pin Function Controller (PFC). Table 9.3 Correspondence between External Pin (MD1 and MD0) Settings and Data Bus Width MD1 MD0 Data Bus Width 1 32 bits 1 0 16 bits 1 8 bits 0 0 Reserved (setting prohibited) |
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