Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

DS72011RB120FPV Datasheet(PDF) 230 Page - Renesas Technology Corp

Part # DS72011RB120FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1196 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DS72011RB120FPV Datasheet(HTML) 230 Page - Renesas Technology Corp

Back Button DS72011RB120FPV Datasheet HTML 226Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 227Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 228Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 229Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 230Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 231Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 232Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 233Page - Renesas Technology Corp DS72011RB120FPV Datasheet HTML 234Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 230 / 1196 page
background image
Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 202 of 1164
REJ09B0321-0200
Area
controller
(CSC)
Access
controller
SDRAM
controller
(SDRAMC)
CS6 to CS0
RD
WR3 to WR0
WAIT
A27 to A0
BC3 to BC0
D31 to D0
SDCS1, SDCS0
SDRAS, SDCAS
SDWE, SDCKE
DQM3 to DQM0
CSMODn
CS1WCNTn
CS2WCNTn
SDRFCNT0/1
SDIR0/1
SDmADR
SDmTR
SDmMOD
[Legend]
Note: n = 0 to 6, m = 0 and 1
CSMODn:
CSn mode register
CS1WCNTn:
CSn wait control register 1
CS2WCNTn:
CSn wait control register 2
CSnCNT:
CSn control register
CSnREC:
CSn recovery cycle setting register
SDCmCNT:
SDRAMCm control register
SDRFCNT0/1: SDRAM refresh control register 0/1
SDIR0/1:
SDRAM initialization register 0/1
SDmADR:
SDRAMm address register
SDmTR:
SDRAMm timing register
SDmMOD:
SDRAMm mode register
SDPWDCNT:
SDRAM power-down control register
SDDPWDCNT: SDRAM deep-power-down control register
SDSTR:
SDRAM status register
SDCKSCNT:
SDRAM clock stop control signal setting register
SDPWDCNT
SDDPWDCNT
SDSTR
SDCKSCNT
CSnCNT
CSnREC
SDCmCNT
Figure 9.1 Block Diagram of BSC



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com