DS72011RB120FPV datasheet(229/1196 Pages) RENESAS

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Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 201 of 1164

REJ09B0321-0200

Section 9 Bus State Controller (BSC)

The bus state controller (BSC) outputs control signals for various types of memory that is

connected to the external address space and external devices. This enables the LSI to connect

directly with SRAM, SDRAM, and other memory storage devices, and external devices.

9.1

Features

1. External address space

• A maximum of 64 Mbytes for the SDRAM and each for areas CS0 to CS6 (256 Mbytes for

CS6)

• Ability to select the data bus width (8, 16, or 32 bits) independently for each address space

2. Normal space interface

• Supports an interface for direct connection to SRAM

• Cycle wait function: Maximum of 31 wait states (maximum of seven wait states for page

access cycles)

• Wait control

 Ability to select the assert/negate timing for chip select signals

 Ability to select the assert/negate timing for the read strobe and write strobe signals

 Ability to select the data output start/end timing

 Ability to select the delay for chip select signals

• Write access modes: One-write strobe and byte-write strobe modes

• Page access mode: Support for page read and page write (64-bit, 128-bit, and 256-bit page

units)

3. SDRAM interface

• Ability to set SDRAM in up to two areas

• Refresh functions

 Auto-refresh (on-chip programmable refresh counter)

 Self-refresh

• Ability to select the access timing (support for low column latency, column latency, and low

active interval settings)

• Initialization sequencer function, power-down function, deep-power-down function, and mode

Figure 9.1 shows a block diagram of the BSC.

DS72011RB120FPV Datasheet(PDF) 229 Page - Renesas Technology Corp