DS72011RB120FPV datasheet(266/1196 Pages) RENESAS

Part #	DS72011RB120FPV

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

PDF	1196 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 238 of 1164

REJ09B0321-0200

Bit

Bit Name

Initial

Value

R/W

Description

3 to 0

ACOSW[3:0] 0000

R/W

AC Characteristics Switch

These bits specify AC characteristics switching.

0000: Does not extend the delay time

0011: Switches characteristics and extends the delay

time

Other than above: Setting prohibited

9.5

Operation

9.5.1

CSC Interface

(1)

Normal Access

Normal read/write operation is used for all bus access when page read/write access is disabled

(PRENB = 0, PWENB = 0). Even when page read/write access is enabled (PRENB = 1, PWENB

= 1), normal read/write operation is employed in cases where page access cannot be used. Figure

9.2 shows the basic operation of the external bus control signals in read operation, and figure 9.3

shows the basic operation of these signals in write operation.

CKIO

Tw1

Tw2

Tend

(Trd)

Twn

Tn1

Tn2

Tnm

A27 to A0

CSn

D31 to D0

Read cycle wait

CS assert wait

RD assert wait

Start enable point

of next bus access

CS delay

cycle during read

Figure 9.2 Basic Bus Timing (Read Operation)

DS72011RB120FPV Datasheet(PDF) 266 Page - Renesas Technology Corp

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