DS72011RB120FPV datasheet(262/1196 Pages) RENESAS

262 / 1196 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 234 of 1164

REJ09B0321-0200

9.4.16

SDRAM Status Register (SDSTR)

SDSTR consists of the status flags that indicate the status of operation during self-refresh,

initialization sequences, power-down mode, deep-power-down mode, and mode register setting.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

000000000000000

RRRRRRRRRRRRRR

000000000000000

RRRRRRRRRRRRRR

—

——————

—

DSRF

DINI

DPWD

DDPD

DMRS

Bit

Bit Name

Initial

Value

R/W

Description

31 to 5



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DSRFST

Self-Refresh Transition/Recovery Status

When set to 1, this bit indicates that a transition to or

recovery from self-refresh operation is in progress for

channel SDRAM0 or SDRAM1.

0: Transition/recovery not in progress

1: Transition/recovery in progress

DINIST

Initialization Status

When set to 1, this bit indicates that an initialization

sequence is in progress for channel SDRAM0 or

SDRAM1. This bit has the same function as the

DINIST bit in SDIR1.

0: Initialization sequence not in progress

1: Initialization sequence in progress

DS72011RB120FPV Datasheet(PDF) 262 Page - Renesas Technology Corp

DS72011RB120FPV Datasheet(HTML) 262 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL