R5F72115D160FPV datasheet(701/1228 Pages) RENESAS

701 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 677 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Receive Enable

Enables or disables the serial receiver of the SCIF.

0: Receiver disabled*

1: Receiver enabled*

Notes:1. Clearing RE to 0 does not affect the receive

flags (DR, ER, BRK, RDF, FER, PER, and

ORER). These flags retain their previous

values.

2. Serial reception starts when a start bit is

detected in asynchronous mode, or

synchronous clock input is detected in

clocked synchronous mode. Select the

receive format in SCSMR and SCFCR and

reset the receive FIFO before setting RE to 1.

REIE

R/W

Receive Error Interrupt Enable

Enables or disables the receive-error (ERI) interrupts

and break (BRI) interrupts. The setting of REIE bit is

valid only when RIE bit is set to 0.

0: Receive-error interrupt (ERI) and break interrupt

(BRI) requests are disabled

1: Receive-error interrupt (ERI) and break interrupt

(BRI) requests are enabled*

Note: * ERI or BRI interrupt requests can be cleared by

reading the ER, BR or ORER flag after it has

been set to 1, then clearing the flag to 0, or by

clearing RIE and REIE to 0. Even if RIE is set

to 0, when REIE is set to 1, ERI or BRI

interrupt requests are enabled. Set so If SCIF

wants to inform INTC of ERI or BRI interrupt

requests during DMA transfer.

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