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R5F72115D160FPV Datasheet(PDF) 702 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 702 Page - Renesas Technology Corp |
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702 / 1228 page  Section 15 Serial Communication Interface with FIFO (SCIF) Rev. 2.00 May. 08, 2008 Page 678 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 2 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on CKE[1:0], the SCK pin can be used for serial clock output or serial clock input. If serial clock output is set in clocked synchronous mode, set the C/ A bit in SCSMR to 1, and then set CKE[1:0]. • Asynchronous mode 00: Internal clock, SCK pin used for input pin (input signal is ignored) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited • Clocked synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited |
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