R5F72115D160FPV datasheet(698/1228 Pages) RENESAS

698 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 674 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

STOP

R/W

Stop Bit Length

Selects one or two bits as the stop bit length in

asynchronous mode. This setting is used only in

asynchronous mode. It is ignored in clocked

synchronous mode because no stop bits are added.

When receiving, only the first stop bit is checked,

regardless of the STOP bit setting. If the second stop

bit is 1, it is treated as a stop bit, but if the second stop

bit is 0, it is treated as the start bit of the next incoming

character.

0: One stop bit

When transmitting, a single 1-bit is added at the end

of each transmitted character.

1: Two stop bits

When transmitting, two 1 bits are added at the end of

each transmitted character.

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

1, 0

CKS[1:0]

R/W

Clock Select

Select the internal clock source of the on-chip baud rate

generator. For further information on the clock source,

bit rate register settings, and baud rate, see section

15.3.8, Bit Rate Register (SCBRR).

00: P

01: P

φ/4

10: P

φ/16

11: P

φ/64

Note: P

φ: Peripheral clock

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