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R5F72115D160FPV Datasheet(PDF) 920 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 920 Page - Renesas Technology Corp |
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920 / 1228 page ![]() Section 21 Flash Memory Rev. 2.00 May. 08, 2008 Page 896 of 1200 REJ09B0344-0200 Table 21.4 (1) Register Configuration Register Name Abbreviation R/W Initial Value Address Access Size Flash code control and status register FCCS R, W* 1 H'00* 2 H'80* 2 H'8000C000 8 Flash program code select register FPCS R/W H'00 H'8000C001 8 Flash erase code select register FECS R/W H'00 H'8000C002 8 Flash key code register FKEY R/W H'00 H'8000C004 8 Flash MAT select register FMATS R/W H'00* 3 H'AA* 3 H'8000C005 8 Flash transfer destination address register FTDAR R/W H'00 H'8000C006 8 Notes: 1. The bits except the SCO bit are read-only bits. The SCO bit is a programming-only bit. (The value which can be read is always 0.) 2. The initial value of the FWE bit is 0 when the FWE pin goes low. The initial value of the FWE bit is 1 when the FWE pin goes high. 3. The initial value at initiation in user mode or user program mode is H'00. The initial value at initiation in user boot mode is H'AA. Table 21.4 (2) Parameter Configuration Name Abbreviation R/W Initial Value Address Access Size Download pass/fail result DPFR R/W Undefined On-chip RAM* 8, 16, 32 Flash pass/fail result FPFR R/W Undefined R0 of CPU 8, 16, 32 Flash multipurpose address area FMPAR R/W Undefined R5 of CPU 8, 16, 32 Flash multipurpose data destination area FMPDR R/W Undefined R4 of CPU 8, 16, 32 Flash erase block select FEBS R/W Undefined R4 of CPU 8, 16, 32 Flash program and erase frequency control FPEFEQ R/W Undefined R4 of CPU 8, 16, 32 Flash user branch address set parameter FUBRA R/W Undefined R5 of CPU 8, 16, 32 Note: * One byte of the start address in the on-chip RAM area specified by FTDAR is valid. |
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