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R5F72115D160FPV Datasheet(PDF) 921 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 921 Page - Renesas Technology Corp |
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921 / 1228 page  Section 21 Flash Memory Rev. 2.00 May. 08, 2008 Page 897 of 1200 REJ09B0344-0200 Table 21.5 Register/Parameter and Target Mode Download Initiali- zation Program- ming Erasure Read RAM Emulation FCCS √ — — — — — FPCS √ — — — — — FECS √ — — — — — FKEY √ — √ √ — — FMATS — — √*1 √*1 √*2 — Programming/ erasing interface registers FTDAR √ — — — — — DPFR √ — — — — — FPFR — √ √ √ — — FPEFEQ — √ — — — — FUBRA — √ — — — — FMPAR — — √ — — — Programming/ erasing interface parameters FMPDR — — √ — — — FEBS — — — √ — — Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target MAT. |
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