R5F72115D160FPV datasheet(922/1228 Pages) RENESAS

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Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 898 of 1200

REJ09B0344-0200

21.4.2

Programming/Erasing Interface Registers

The programming/erasing interface registers are as described below. They are all 8-bit registers

that can be accessed in bytes.

(1)

Flash Code Control and Status Register (FCCS)

FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence

during programming or erasing flash memory and the download of the on-chip program.

Bit:

Initial value:

R/W:

7654321

1/0

RRRRRRR

(R)/W

FWE

MAT

FLER

SCO

Bit

Bit Name

Initial

Value

R/W

Description

FWE

1/0

Flash Programming Enable

Monitors the level which is input to the FWE pin that

performs hardware protection of the flash memory

programming or erasing. The initial value is 0 or 1

according to the FWE pin state.

0: When the FWE pin goes low (in hardware protection

state)

1: When the FWE pin goes high

MAT

1/0

MAT Bit

Indicates whether the user MAT or user boot MAT is

selected.

0: User MAT is selected

1: User boot MAT is selected

⎯

Reserved

This bit is always read as 0. The write value should always

be 0.

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