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R5F72115D160FPV Datasheet(PDF) 932 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 932 Page - Renesas Technology Corp |
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932 / 1228 page ![]() Section 21 Flash Memory Rev. 2.00 May. 08, 2008 Page 908 of 1200 REJ09B0344-0200 (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. Since the user branch function is supported, the user branch destination address must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings. (2.1) Flash Programming/Erasing Frequency Parameter (FPEFEQ: General Register R4 of CPU) This parameter sets the operating frequency of the CPU. The flash programming/erasing frequency I φ of this LSI is limited to 32 to 40 MHz. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 0 ---------------- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ---------------- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ---------------- F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 |
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