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R5F72115D160FPV Datasheet(PDF) 930 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 930 Page - Renesas Technology Corp |
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930 / 1228 page ![]() Section 21 Flash Memory Rev. 2.00 May. 08, 2008 Page 906 of 1200 REJ09B0344-0200 Table 21.6 Usable Parameters and Target Modes Name of Parameter Abbrevia- tion Down- load Initiali- zation Pro- gram- ming Erasure R/W Initial Value Allocation Download pass/fail result DPFR √ — — — R/W Undefined On-chip RAM* Flash pass/fail result FPFR — √ √ √ R/W Undefined R0 of CPU Flash programming/ erasing frequency control FPEFEQ — √ — — R/W Undefined R4 of CPU Flash user branch address set FUBRA — √ — — R/W Undefined R5 of CPU Flash multipurpose address area FMPAR — — √ — R/W Undefined R5 of CPU Flash multipurpose data destination area FMPDR — — √ — R/W Undefined R4 of CPU Flash erase block select FEBS — — — √ R/W Undefined R4 of CPU Note: * One byte of start address of download destination specified by FTDAR (1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the area as much as 3 kbytes starting from the start address specified by FTDAR. For the address map of the on-chip RAM, see figure 21.10. The download control is set by using the programming/erasing interface registers. The return value is given by the DPFR parameter. (a) Download Pass/Fail Result Parameter (DPFR: One Byte of Start Address of On-Chip RAM Specified by FTDAR) This parameter indicates the return value of the download result. The value of this parameter can be used to determine if downloading is executed or not. Since the confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the start address of the on-chip RAM area specified by FTDAR to a value other than the return value of download (for example, H'FF) before the download start (before setting the SCO bit to 1). For |
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