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R5F72115D160FPV Datasheet(PDF) 933 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 933 Page - Renesas Technology Corp |
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933 / 1228 page ![]() Section 21 Flash Memory Rev. 2.00 May. 08, 2008 Page 909 of 1200 REJ09B0344-0200 Bit Bit Name Initial Value R/W Description 31 to 16 ⎯ Undefined R/W Unused Return 0. 15 to 0 F15 to F0 Undefined R/W Frequency Set Set the operating frequency I φ of the CPU following the calculation below. I φ = F[15:0] × 104 Hz 1. Round it off to the digit of 1 kHz, and round down the lower digits. 2. For example, when I φ = 33.333 MHz, set as follows: (1) I φ = 3333 × 104 Hz (2) F[15:0] = 3333 (H'0D05) (3) Set R4 (FPEFEQ) to H'00000D05. (2.2) Flash User Branch Address Setting Parameter (FUBRA: General Register R5 of CPU) This parameter sets the user branch destination address. The user program which has been set can be executed in specified processing units when programming and erasing. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 0 ---------------- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ---------------- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UA31 UA30 UA29 UA28 UA27 UA26 UA25 UA24 UA23 UA22 UA21 UA20 UA19 UA18 UA17 UA16 UA15 UA14 UA13 UA12 UA11 UA10 UA9 UA8 UA7 UA6 UA5 UA4 UA3 UA2 UA1 UA0 |
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