R5F72115D160FPV datasheet(945/1228 Pages) RENESAS

945 / 1228 page

Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 921 of 1200

REJ09B0344-0200

(1)

SCIF Interface Setting by Host

When boot mode is initiated, this LSI measures the low period of asynchronous SCIF-

communication data (H'00), which is transmitted consecutively by the host. The SCIF

transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate

of transmission by the host by means of the measured low period and transmits the bit adjustment

end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign

(H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not

executed normally, boot mode is initiated again (reset) and the operation described above must be

executed. The bit rate between the host and this LSI is not matched because of the bit rate of

transmission by the host and system clock frequency of this LSI. To operate the SCIF normally,

the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.

The system clock frequency which can automatically adjust the transfer bit rate of the host and the

bit rate of this LSI is shown in table 21.7. Boot mode must be initiated in the range of this system

clock.

Start

bit

Stop bit

Measure low period (9 bits) (data is H'00)

High period of

at least 1 bit

Figure 21.7 Automatic Adjustment Operation of SCIF Bit Rate

Table 21.7

Peripheral Clock (P

φ) Frequency that Can Automatically Adjust Bit Rate of

This LSI

Host Bit Rate

Peripheral Clock (P

φ) Frequency That Can Automatically Adjust LSI's Bit

Rate

9,600 bps

32 to 40 MHz

19,200 bps

32 to 40 MHz

R5F72115D160FPV Datasheet(PDF) 945 Page - Renesas Technology Corp