H8SLASH3021 datasheet(345/712 Pages) RENESAS

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10. Watchdog Timer

Rev.2.00 Mar. 22, 2007 Page 321 of 684

REJ09B0352-0200

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources,

obtained by prescaling the system clock (

φ), for input to TCNT.

Bit 2

CKS2

Bit 1

CKS1

Bit 0

CKS0

Description

φ/2

(Initial value)

φ/32

φ/64

φ/128

φ/256

φ/512

φ/2048

φ/4096

10.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable*

1 register that indicates when a reset signal has been

generated by watchdog timer overflow, and controls external output of the reset signal.

Bit

Initial value

Read/Write

WRST

R/(W)

RSTOE

R/W

—

Watchdog timer reset

Indicates that a reset signal has been generated

Reserved bits

Reset output enable*3

Enables or disables external output of the reset signal

Bits 7 and 6 are initialized by input of a reset signal at the

RES pin. They are not initialized by

reset signals generated by watchdog timer overflow.

Notes: 1. RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on

2. Only 0 can be written in bit 7 to clear the flag.

3. With the mask ROM version, enable and disable can be set. With the F-ZTAT version,

do not set enable.

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