H8SLASH3021 datasheet(346/712 Pages) RENESAS

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10. Watchdog Timer

Rev.2.00 Mar. 22, 2007 Page 322 of 684

REJ09B0352-0200

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that

TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip

internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the

RESO pin*1 to

initialize external system devices.

Bit 7

WRST

Description

[Clearing condition]

(Initial value)

(1) Cleared to 0 by reset signal input at

RES pin

(2) Cleared by reading WRST when WRST = 1, then writing 0 in

WERST

[Setting condition]

Set when TCNT overflow generates a reset signal during

watchdog timer operation

Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the

RESO pin*1 of

the reset signal generated if TCNT overflows during watchdog timer operation.

Bit 6

RSTOE

Description

Reset signal is not output externally

(Initial value)

Reset signal is output externally*

Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.

Notes: 1. Mask ROM version. Dedicated FWE input pin for F-ZTAT version.

2. Mask ROM version. Do not set to 1 with the F-ZTAT version.

H8/3021 Datasheet(PDF) 346 Page - Renesas Technology Corp