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H8/3021 Datasheet(PDF) 343 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 343 Page - Renesas Technology Corp |
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343 / 712 page  10. Watchdog Timer Rev.2.00 Mar. 22, 2007 Page 319 of 684 REJ09B0352-0200 10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable* 1 register. Its functions include selecting the timer mode and clock source. Bit Initial value Read/Write 7 OVF 0 R/(W) 6 WT/ IT 0 R/W 5 TME 0 R/W 4 — 1 — 3 — 1 — 0 CKS0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W Overflow flag Status flag indicating overflow Clock select These bits select the TCNT clock source Timer mode select Selects the mode Timer enable Selects whether TCNT runs or halts Reserved bits *2 Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Notes: 1. TCSR is write-protected by a password. For details see section 10.2.4, Notes on Register Access. 2. Only 0 can be written to clear the flag. |
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