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H8/3021 Datasheet(PDF) 467 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 467 Page - Renesas Technology Corp |
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467 / 712 page  14. RAM Rev.2.00 Mar. 22, 2007 Page 443 of 684 REJ09B0352-0200 14.2 System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 — 1 — 0 RAME 1 R/W Software standby Standby timer select 2 to 0 User bit enable NMI edge select Reserved bit RAM enable bit Enables or disables on-chip RAM SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register. Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip RAM is enabled (Initial value) |
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