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H8/3021 Datasheet(PDF) 468 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 468 Page - Renesas Technology Corp |
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468 / 712 page  14. RAM Rev.2.00 Mar. 22, 2007 Page 444 of 684 REJ09B0352-0200 14.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip RAM when addressing the addresses shown in Table 14.1 in each operation mode. When the RAME bit is cleared to 0 in modes 1, 3, 5, and 6 (expanded modes), external address space is accessed. When the RAME bit is cleared to 0 in mode 7 (single-chip modes), the on-chip RAM is not accessed. Read operation always reads H'FF and disables writing. The on-chip RAM is connected to the CPU by a 16-bit wide data bus and can be read and written on a byte or a word basis. Byte data can be accessed in two states using the higher 8 bits of the data bus. Word data beginning from an even address can be accessed in two states using the 16-bit data bus. |
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