H8SLASH3021 datasheet(478/712 Pages) RENESAS

478 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 454 of 684

REJ09B0352-0200

15.3

Pin Configuration

The flash memory is controlled by means of the pins shown in table 15.1.

Table 15.1

Pin Configuration

Pin Name

Abbreviation

I/O

Function

Reset

RES

Input

Reset

Flash write enable

FWE

Input

Flash program/erase protection by hardware

Mode 2

MD2

Input

Sets LSI operating mode

Mode 1

MD1

Input

Sets LSI operating mode

Mode 0

MD0

Input

Sets LSI operating mode

Transmit data

TxD1

Output

Serial transmit data output

Receive data

RxD1

Input

Serial receive data input

15.4

The registers*

1 used to control the on-chip flash memory when enabled are shown in table 15.2.

Table 15.2

Abbreviation

R/W

Initial Value

Address*

Flash memory control register 1

FLMCR1*

R/W

H'00*

H'FF40

Flash memory control register 2

FLMCR2*

H'00

H'FF41

Erase block register 1

EBR1*

R/W

H'00

H'FF42

Erase block register 2

EBR2*

R/W

H'00

H'FF43

RAM emulation register

RAMER*

R/W

H'F0

H'FF47

Notes: 1. FLMCR1, FLMCR2, EBR1, and EBR2, and RAMER are 8-bit registers.

Byte access must be used on these registers (do not use word or longword access).

These registers are for use exclusively by the flash memory version, and are not

provided in the mask ROM version. Reads to the corresponding addresses in the mask

ROM version will always return 1, and writes to these addresses are invalid.

Access to address H'FF44 to H'FF46 and H'FF48 to H'FF4F (lower 16 bits) is

prohibited.

2. Lower 16 bits of the address.

3. When a high level is input to the FWE pin, the initial value is H'80.

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